1. Field of the Invention
This invention relates to the formation of integrated circuit structures on semiconductor substrates. More particularly, this invention relates to a process for forming a cobalt silicide (CoSi.sub.2) conductive layer on an integrated circuit structure.
2. Description of the Related Art
In the formation of integrated circuit structures, and particularly in the formation of MOS devices using polysilicon gate electrodes, it has become the practice to provide a metal silicide layer over the polysilicon gate electrode, and over the source/drain regions of the silicon substrate, to facilitate electrically and metallurgically connecting the silicon to metal interconnects. Thus, for example, a titanium metal layer is usually blanket deposited over the polysilicon gate electrode and the source/drain regions of the silicon substrate, as well as over the silicon oxide insulation regions of the substrate, e.g., the field oxide regions. The structure is then heated sufficiently to cause the titanium in contact with the silicon to react, thereby forming titanium silicide, e.g., heated to about 700.degree. C., while the titanium over the silicon oxide does not react. The unreacted titanium is then removed, leaving only titanium silicide over the silicon source/drain regions of the substrate and over the polysilicon gate electrode. The resulting titanium silicide is then further annealed at a higher temperature, e.g., higher than about 750.degree. C., to cause the earlier formed titanium silicide, formed as a high resistivity C49 phase, to convert to the more electrically desirable (lower resistivity) C54 phase (the structure is not initially annealed at the higher (C54-forming) temperature because the titanium tends to also react with the silicon oxide insulation at the higher temperature). A metal layer, such as tungsten, aluminum, etc. can then be deposited over the titanium silicide layer.
However, as the sizes of integrated circuit structures have continued to become smaller and smaller, problems have arisen with the continued use of titanium silicide, particularly in the formation of narrow lines, because the higher resistivity C49 phase of titanium silicide tends to predominate on narrower lines. This is apparently due to the failure of the C49 phase to convert to the low resistivity C54 phase when the line width approaches the grain size of the C49 phase. It has, however, been found that cobalt silicide (CoSi.sub.2) is not subject to the same phase problems when used in forming narrow lines. However, cobalt does not reduce oxide as well as titanium, and thus the cleanliness of the semiconductor substrate is much more critical if cobalt is used to form the desired metal silicide. Furthermore, the variation in oxidation rates of differently doped silicon substrates can also cause cobalt silicide formation to be substrate dependent.
Berti et al., in an article entitled "A MANUFACTURABLE PROCESS FOR THE FORMATION OF SELF ALIGNED COBALT SILICIDE IN A SUB MICROMETER CMOS TECHNOLOGY", published on pages 267-273 of the VMIC Conference held in Santa Clara, Calif. in 1992, state that processing temperature, resistivity, contact resistance, junction leakage, and stress are all lower when using cobalt silicide instead of titanium silicide. However, they report that the difficulty in implementing cobalt silicide in a manufacturing environment has been due to the inability to repeatedly avoid unwanted cobalt silicide overgrowth on the oxide spacers (which can result in electrical shorting) while simultaneously forming thick and uniform cobalt silicide. They reported that the problem of cobalt silicide overgrowth on the oxide portions of the integrated circuit structure could be eliminated by the reactive sputtering of a capping layer of titanium nitride over the layer of cobalt prior to the annealing step to form cobalt silicide.
A later article by Yamazaki et al., entitled "21 psec switching 0.1 .mu.m-CMOS at room temperature using high performance Co salicide process", published on pages 6.7.1-6.7.3 of 906 IDEM 93, reports that in conventional cobalt salicide (self-aligned silicide), the gate sheet resistance increased below a 1.0 .mu.m gate length because the cobalt layer was oxidized during the first silicidation annealing. They reported that the use of a titanium nitride capping layer over the cobalt salicide effectively avoided the oxidation and drastically improved the gate length dependence of the gate sheet resistance, resulting in the achievement of a gate delay of 21 ps for a 0.1 .mu.m gate length and 19 ps for a 0.075 .mu.m gate length.
It has also been proposed to provide a capping layer of titanium over the cobalt layer prior to the silicidation step. Wang et al., in an article entitled "New CoSi.sub.2 SALICIDE Technology for 0.1 .mu.m Processes and Below", published on pages 17 and 18 of the 1995 Symposium on VLSI Technology Digest of Technical Papers, report that the use of titanium over cobalt in the formation of cobalt silicide provides a much smoother CoSi.sub.2 /poly interface than the conventional process with less sensitivity to pre-sputtering surface conditions and annealing conditions. They also indicate, however, that it is difficult to form thin CoSi.sub.2 on a sub-0.1 .mu.m poly-Si runner using the conventional process, but that the use of a thin titanium capping layer improves both the formation and thermal stability of sub-0.1 .mu.m CoSi.sub.2 /Poly stacks.
While the foregoing articles indicate superior results in the use of cobalt silicide (CoSi.sub.2) for 0.1 .mu.m line technology when the cobalt layer is capped with either titanium or titanium nitride, it has been found that there still exists problems with the use of even capped cobalt silicide, at least with respect to the uniformity of the thickness of cobalt silicide (CoSi.sub.2) formed over the polysilicon gate electrode. An example of this is illustrated in prior art FIG. 1. FIG. 1 shows a portion of an integrated circuit structure comprising a silicon substrate 2 having a conventional NMOS structure formed thereon, it being understood that the problem is not limited to the construction of NMOS devices, but is also applicable to PMOS devices. In the illustrated MOS structure, N+ source/drain regions 4 and 6 are formed in P type silicon substrate 2 adjacent field oxide portions 8, with a gate oxide layer 10 and a polysilicon gate electrode 12 formed over silicon substrate 2 in between source/drain regions 4 and 6, and with oxide spacers 13 formed on the sidewalls of polysilicon gate electrode 12. FIG. 1 further shows cobalt silicide (CoSi.sub.2) segments 14 and 16 formed respectively over source/drain regions 4 and 6 and cobalt silicide segment 18 formed over the top surface of polysilicon gate electrode 12. In this conventional prior art formation of cobalt silicide, wherein the substrate and/or the cobalt layer is not sufficiently protected from exposure to oxygen prior to the annealing step, the silicide formation will be degraded. For example, it will be noted in prior art FIG. 1 that the end portions 19 of cobalt silicide segment 18 on the top surface of polysilicon gate electrode 12 adjacent oxide spacers 13 are thinner than the remainder of cobalt silicide segment 18.